• AlGaN/GaN HEMTs on Silicon Carbide Substrates

Sponsored Links

  •   
  • FileName: 13-2.pdf [read-online]
    • Abstract: AlGaN/GaN HEMTs on Silicon Carbide Substratesfor Microwave Power OperationRichard Lossy1, Nidhi Chaturvedi1, Peter Heymann1, Klaus Köhler2,Stefan Müller2 and Joachim Würfl11Ferdinand-Braun-Institut für Höchstfrequenztechnik, Albert-Einstein-Straße 11, 12489 Berlin, Germany

Download the ebook

AlGaN/GaN HEMTs on Silicon Carbide Substrates
for Microwave Power Operation
Richard Lossy1, Nidhi Chaturvedi1, Peter Heymann1, Klaus Köhler2,
Stefan Müller2 and Joachim Würfl1
1
Ferdinand-Braun-Institut für Höchstfrequenztechnik, Albert-Einstein-Straße 11, 12489 Berlin, Germany
2
Fraunhofer-Institut für Angewandte Festkörperphysik, Tullastraße 72, 79108 Freiburg, Germany
Phone: +49 30 63922630 Fax: +49 30 63922685 e-mail: [email protected]
Keywords: Gallium nitride, HEMT, power semiconductor
ABSTRACT bination with the spontaneous polarization effect
Results from technology and microwave results in high sheet carrier densities in the
characterization of large periphery Al- 1×1013 cm-2 range. Furthermore, SiC as a sub-
GaN/GaN power HEMTs on insulating strate material provides an excellent thermal
SiC substrates are presented. The influence of conductivity, comparable to copper. This is
processing steps on device performance is mandatory for effective heat removal in high
discussed. DC characteristics reveal current power applications. All these features together
densities above 1.2 A/mm and extrinsic trans- account for devices with very high absolute mi-
conductances of 275 mS/mm. A power density crowave output power levels.
of 5.2 W/mm @ 2 GHz is obtained for devices
up to 2 mm gate width. The maximum power TECHNOLOGY AND DC CHARACTERISATION
level achieved on-wafer is 13.8 W @ 2 GHz The Al0.25Ga0.75N/GaN HEMT structures
for 4 mm wide devices. A hybrid amplifier were grown in a multiwafer MOCVD (6x2”)
using packaged 4 mm devices delivers 15.1 W. reactor yielding high throughput and reproduci-
bility. Device fabrication was accomplished us-
INTRODUCTION ing i-line stepper lithography. However, without
As promising candidates for future micro- certain technological precautions the transpar-
wave power devices, GaN-based high-electron ency of SiC-wafers with AlGaN/GaN epitaxy
mobility transistors (HEMTs) have attracted impedes a precise and reliable image alignment
much research interest. Their potential is due to with respect to wafer surface and orientation.
advantageous material properties such as the Therefore, special processing sequences were
wide band gap leading to high breakdown volt- developed to allow the proper exposure. A so-
age and high saturated-electron drift velocity. phisticated metallization scheme was employed
Also, the existence of AlGaN/GaN heterostruc- for fabrication of the ohmic contacts that pre-
tures with high conduction band offsets in com- serves pattern delineation during rapid thermal
annealing at 830°C [1-3].
Fig. 1: AlGaN/GaN
HEMTs on a 2” wafer
(left) comprising parallel
transistor fingers (center)
and detail of the gate
feeding (right) also show-
ing the transistor channel
and arch of the air bridge
structure.
Copyright 2003 GaAsMANTECH, Inc. 2003 International Conference on Compound Semiconductor Mfg.
Gate contacts were made using Pt/Au metal- Table I:
lization. A gate length of 0.5 µm was defined Maximum Device Temperature
with stepper lithography, shorter gate lengths Device Chip Gate Substrate Tmax
down to 0.25 µm were defined by electron beam Size Package Pitch /°C
lithography (ZBA23-40kV). Large devices with 16x250 50 SiC 143
different gate widths ranging up to 4 mm were 16x250 100 SiC 113
fabricated using an air bridge technology (Fig. 16x250 * 50 SiC 92
1). 8x125 * 50 SiC 77
In order to optimize thermal and electrical 16x250 * 50 Sapphire 679
properties, power cell design variations have * chip without housing fixed on base plate
been integrated on chip. Different scaling strate- Simulated maximum device temperatures for different
gies regarding the number and width of the gate transistor geometries and substrates: Base plate tem-
perature held at To=27°C.
fingers or the gate pitch, i.e. spacing between re-
peating cell structures have been implemented. 2) A gate pitch of 50 µm is sufficient to achieve
DC measurements revealed a saturated drain tolerable device temperature.
current of IDSS=1.2 A/mm (VG= +2V). Due to the 3) The thermal resistance of the chip package
excellent contact resistance (0.3 Ωmm), the cannot be neglected.
source-gate resistance is 0.85 Ωmm. This leads
to a calculated intrinsic gm,max of 360 mS/mm PASSIVATION
(extrinsic 275 mS/mm) and an on-resistance of For AlGaN/GaN-HEMTs it is known that
Ron= 2 Ωmm. the maximum power levels under rf-operation
degrade substantially compared to the expecta-
THERMAL SIMULATION tions based on DC measurements. This degrada-
Thermal simulations were performed using a tion could be reduced significantly if the HEMT
three dimensional finite-element model in the surface is passivated. As an example the rf-
Nastran-Patran software package. The goal was power recovery after passivation is given in Fig.
to extract optimized device designs for a given 2, where the passivated HEMTs show an average
packaging technique. The GaN chip dimensions increase of the maximum rf-power by a factor of
used for simulation were 1.5 × 2 mm² with a 3 after passivation using SiNx.
device layout using parallel gate fingers. The According to the general understanding this
active element of heat dissipation was repre- improvement is mainly due to a reduction of
sented by a 2-D planar heat source at each of the electrically active surface traps. However, due to
gate fingers. For better comparison, the different the effect of spontaneous polarization on the
device geometries used the same dissipated heat 2DEG carrier concentration, the mechanical
per gate width (5 W/mm). strain of the passivation layer might influence
The chip package was a standard CuW RF device performance. We checked this by com-
power transistor package with a thermal conduc- paring tensile and compressive types of SiNx
tivity of 180 W/mK. For die attachment a Au/Sn
eutectic solder was used. 5
The largest device with a total of 4 mm gate
width consisted of 16 gate fingers each having a 4
after passivation
width of 250 µm (referred to 16x250). The dis-
Pout (W/mm)
3
tance between the individual gate fingers was
50 µm pitch for most transistors.
2
Table 1 compares the simulation results of
the different geometries. The following conclu- 1 before passivation
sions can be drawn:
1) Using SiC-substrates the temperature rise is 0
not higher than 120°C for all geometries un- -30 -20 -10 0 10 20 30
der consideration. Position / mm
Fig. 2: Comparison of load pull power results before
and after passivation for HEMTs at different radial
position on the wafer. The gate width is 100 µm.
Copyright 2003 GaAsMANTECH, Inc. 2003 International Conference on Compound Semiconductor Mfg.
passivation layers. No differences in the rf- is switched simultaneously away from a steady
power after passivation could be found. bias point to the point where the current had to
The recovery of the rf-power after passiva- be measured for a very short time (pulse length:
tion is substantial, but far not complete. This can 0,2 µsec, pulse separation 1 msec). Therefore
be demonstrated by pulsed I/V-measurements of trapped electrons and holes cannot follow these
the passivated devices. The related mechanisms fast changes. They are “frozen” at those biasing
are generally referred to as the gate-lag and conditions where the pulsing starts from.
drain-lag phenomena [4, 5]. The gate-lag phe- The measurement conditions according to
nomenon is associated with traps in the vicinity fig. 3a highlight the influence of traps in the
of the gate, the drain lag phenomenon is related vicinity of the gate space charge region (gate-
to backgating effects due to electron trapping in lag). At the steady bias point of VGS = 0V and
the buffer layers [5]. VDS = 0V practically no traps are activated since
Pulsed measurements on passivated devices the gate space charge region is very small. Puls-
as shown in Fig. 3 visualize these trapping ef- ing from these conditions nearly represents the
fects. During pulsing the gate and drain voltage ideal I/V- characteristics as it would appear in
1.2
the absence of any traps. However, for a steady
(Vgs0=-4.0v,Vds0=0.0v)
gate bias close to pinch off the gate space charge
1.0 (Vgs0=0.0v,Vds0=0.0v) region is expanded, therefore traps in the vicinity
of the gate, especially at the surface are acti-
0.8
vated. The corresponding pulse measurements
Ids(A/mm)
0.6 reflect these conditions as shown in fig. 3a
(black curves).
0.4 If the steady bias point of the drain source
0.2
voltage (VDS) is set to higher values (fig. 3b,
black curves) these measurement conditions
0.0 additionally consider the effect of traps located
0 5 10 15 20 25
in the buffer (drain-lag). Due to the band bend-
Vds(V) ing resulting from this bias point also traps in the
Fig. 3a: Pulsed measurement of I/V-characteristics: buffer are activated, leading to dynamic con-
Steady bias points: ditions as shown by the black curves. If the de-
VGS = 0 V; VDS = 0 V vice is biased at large signal microwave condi-
VGS = -4 V; VDS = 0 V tions the effectively usable I/V-characteristics is
gate voltage sweep: -4 V .... +1 V close to these conditions. For comparison the
static I/V-characteristics is also given in fig. 3b
1.2
(gray curve). The difference between these
1.0 static
curves clearly demonstrates further potential of
Dynamic improvements if material quality and processing
0.8 (Vgs0=-4.0v,Vds0=20v)
is optimized accordingly.
Ids(A/mm)
0.6
MICROWAVE CHARACTERISTICS
0.4 S-parameters of the microwave power tran-
sistors were measured up to 50 GHz. For the
0.2
LG=0.3 µm gates a current gain cut-off frequency
0.0
ft of 37 GHz was obtained. Therefore, the LG x ft
0 5 10 15 20 25 product is 10 GHz µm. This compares well with
Vds(V) the 0.5 µm gates for which we measured
Fig. 3b: Comparison of static ( ) and dynamic ( )
ft =21 GHz. Devices having 100µm gate width
output characteristics. Steady bias point for reveal fmax= 74 GHz. For larger devices
pulsed measurement: (gate width 4 mm, LG= 0.3 µm) fmax reduces to
VGS = -4V; VDS = 20 V 31 GHz.
gate voltage sweep: -4 V .... +1 V
Copyright 2003 GaAsMANTECH, Inc. 2003 International Conference on Compound Semiconductor Mfg.
1000
2...16x50
100
Re (Z) (Ω)
8x125
16x125 16x250
10
PTF 10107
LDMOS(Ericson)
1
0 5 10 15
Power (W)
Fig. 4: Scaling of the output impedance with gate
width at 2 GHz. The insets indicate the number of
transistor fingers times finger width. Fig. 5: Single stage amplifier with GaN-power HEMT
Large signal on-wafer microwave measure- output power in this configuration is 41,8 dBm
ments were made at 2 and 10 GHz using passive (15,1 W) at 2 GHz.
load-pull systems in class A operation. For a
device with a gate width of 4 mm (16x250µm) CONCLUSION
the maximum output power of 13.8 W @ 2GHz A technology based on stepper lithography
could be achieved. The corresponding efficiency was developed for the fabrication of large Al-
(PAE) was 53 %, gain is 25 dB and decreased to GaN/GaN HEMTs on SiC substrate. Devices of
21 dB in saturation. The highest power density different size with a gate width up to 4 mm were
measured was 5.2 W/mm and could be obtained characterized. DC characterization yielded a
on devices ranging from 100 µm width up to saturated drain current of 1.2 A/mm and an in-
2 mm. 4 mm wide devices deviate from this lin- trinsic transconductance of 360 mS/mm. Load-
ear scaling and in this case the output power was pull measurements were performed at 2 and
reduced to 66 % of the expected value. Load-pull 10 GHz. From these devices a power density of
measurements at 10 GHz reveal a maximum 5.2 W/mm was achieved at 2GHz. The maxi-
power density of 4.5 W/mm. This slight reduc- mum power level obtained was 13.8 W for a
tion may be explained by device parasitics at 4 mm wide device, showing a power gain of
higher frequencies. 25 dB.
The large signal output impedance at 2 GHz
was calculated from the Γ-load values of the load ACKNOWLEDGMENT
pull measurements. The results for devices up to Financial support by the Bundesministerium
4 mm gate width are given in Fig. 4, showing a für Bildung und Forschung under contract
scaling with device size and thus device power. 01BM155 is gratefully acknowledged.
For a given power level of 5 W the output im-
pedance of GaN-devices by far exceeds that of REFERENCES
their LDMOS counterparts. High output impe- [1] R. Lossy, N. Chaturvedi, J. Würfl, St. Müller, K.Köhler,
physica status solidi (a)Vol.194 (2), 2002.pp.460-463.
dances are favorable for combining power cells [2] R. Lossy,. J. Hilsenbeck, J. Würfl, K. Köhler and H. Obloh,
to high power microwave amplifiers. Proc. Int. Workshop on Nitride Semiconductors 2000, IPAP
Conference Series 1, p942-945
[3] J. Hilsenbeck, E.Nebauer, J. Würfl, G. Tränkle, and H.Obloh,
POWER AMPLIFIER El.Lett. 36, 981(2000)
Transistors of 4 mm gate width were diced [4] S. C. Binari, K. Ikossi, J.A. Roussos, W. Kruppa, D. Park,
H.B. Dietrich, D.D. Koleske, A. E. Wickenden, R.L. Henry,
and packaged in a commercial CuW-package "Trapping effects and microwave power performance in Al-
using AuSn chip-bonding. The packaged devices GaN/GaN HEMTs" IEEE Trans. on Electron Devices, vol.
were mounted in a single stage amplifier de- 48, no.3 pp. 465-471, March 2001
[5] S. De Meyer, C. Charbonniaud, R. Quere, M. Campoveccio, J,
signed for operation at frequencies of Würfl, R. Lossy, "Mechanism of power density degradation
1…2.5 GHz at 50 Ω (Fig. 5). The maximum due to trapping effects in AlGaN/GaN HEMTs", paper ac-
cepted for presentation at the 2003 International Microwave
Symposium, Philadelphia, USA
Copyright 2003 GaAsMANTECH, Inc. 2003 International Conference on Compound Semiconductor Mfg.


Use: 0.3537